A. Field of the Invention
The present invention relates to a semiconductor device and semiconductor device manufacturing method.
B. Description of the Related Art
High breakdown voltage discrete power devices fulfil a central role in power conversion devices. As examples of this kind of power devices, there are an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET), and the like. An IGBT, being a conductivity modulating type of bipolar device, has a low on-state voltage compared with that of a MOSFET, which is a unipolar device, because of which IGBTs are particularly widely used in switching circuits, and the like, in which are mounted high breakdown voltage devices whose on-state voltage is liable to be high.
Furthermore, in order to adapt the power conversion device so as to be a matrix converter with higher conversion efficiency, bidirectional switching devices are necessary. A reverse blocking IGBT having reverse breakdown voltage of the same extent as the forward breakdown voltage is attracting attention as a semiconductor device configuring this bidirectional switching device. The reason for this is that the bidirectional switching device can easily be configured by the reverse blocking IGBT being connected in anti-parallel. The reverse blocking IGBT is a device wherein the p-n junction between the collector region and drift region in a normal IGBT is improved so as to be able to maintain reverse blocking voltage using a termination structure with high voltage withstanding reliability. Because of this, the reverse blocking IGBTs are suitable as switching devices mounted in the AC-AC power converting matrix converter or in a DC-AC converting multilevel inverter.
Referring to FIG. 12, a description will be given hereafter of the structure of a heretofore known reverse blocking IGBT. FIG. 12 is a sectional view showing a main portion of the heretofore known reverse blocking IGBT. As shown in FIG. 12, the reverse blocking IGBT is also such that, in the same way as a normal IGBT, an active region 110 is provided in the vicinity of the center of a chip, and an edge termination structure portion 120 is provided on an outer peripheral side surrounding the active region 110. Further, the reverse blocking IGBT is characterized by having an isolation region 130 enclosing the outer side of the edge termination structure portion 120. The isolation region 130 has as a main region a p+ type isolation layer 31 for linking one main surface and the other main surface of an n− type semiconductor substrate with a p-type region.
In order to form the p+ type isolation layer 31 using thermal diffusion of a p-type impurity from the one main surface of the n− type semiconductor substrate, it is necessary to form the p+ type isolation layer 31 extremely deep, which involves a thermal diffusion drive at a high temperature for a long time. Owing to the p+ type isolation layer 31, the structure can be such that the termination of a p-n junction plane between a p-type collector region 10 and n− type drift region 1, which is a reverse direction voltage withstanding junction, is not exposed on a chip side end surface 12 that forms the cutting plane when fabricating chips. Furthermore, the p-n junction plane between the p-type collector region 10 and n− type drift region 1, as well as not being exposed on the chip side end surface 12, is exposed on a substrate surface (substrate front surface side surface) 13 of the edge termination structure portion 120 protected by a dielectric 14. Because of this, it is possible to increase reverse direction voltage withstanding reliability.
The active region 110 is a region forming a path for the main current of a vertical IGBT including a front surface side structure formed of the n− type drift region 1, a p-type base region 2, an n+ type emitter region 3, a gate dielectric 4, a gate electrode 5, an interlayer dielectric 6, an emitter electrode 9, and the like, and a back surface structure of the p-type collector region 10, a collector electrode 11, and the like. Furthermore, the depth of a termination p-type base region (an outermost p-type base region of the active region 110) 2-1 of a termination portion 110a of the active region 110 near the edge termination structure portion 120 is larger than that of the p-type base region 2 inward of the termination p-type base region 2-1. An n-type high concentration region 1a with resistivity lower than that of the n− type drift region 1, and of a depth larger than that of the p-type base region 2, is formed in a surface layer of the n− type drift region 1 below the gate electrode 5 between neighboring p-type base regions 2, thus reducing the on-state voltage.
The edge termination structure portion 120 includes a p-type guard ring 7 and a field plate 8 for relaxing the electrical field intensity, which is liable to become high when a forward direction voltage is applied (the collector electrode 11 is connected to a positive electrode while the emitter electrode 9 is connected to a negative electrode) and when reverse direction voltage is applied (the collector electrode 11 is connected to a negative electrode while the emitter electrode 9 is connected to a positive electrode), and the dielectric 14 as a termination protection film of the p-n junction exposed on the substrate surface 13. The p-type guard ring 7, preferably being formed deeper than the p-type base region 2, is formed simultaneously with the termination p-type base region 2-1.
Meanwhile, when using a normal IGBT in the previously described inverter and the like, it is necessary to connect a free wheeling diode (hereafter abbreviated to FWD) in anti-parallel to the IGBT. Also, the FWD is such that, in order to improve reverse recovery characteristic, the carrier lifetime of the drift region of the FWD (hereafter referred to simply as lifetime) is sometimes adjusted so as to vary locally.
A sectional view of this kind of FWD wherein the lifetime locally varies is shown in FIG. 15(a). FIG. 15 illustrates a sectional structure and lifetime profile of a heretofore known diode. FIG. 15(a) is the sectional structure of the FWD, while FIG. 15(b) shows the profile (distribution), with the depth direction of a semiconductor substrate configuring the FWD as the horizontal axis, and the lifetime as the vertical axis. The structure of the FWD of FIG. 15 is described hereafter. In this semiconductor diode (FWD), a p-type semiconductor region 105 is provided in a surface layer on the front surface side of an n− type semiconductor substrate with a low n− type impurity concentration. An anode electrode 109 is provided in contact with the front surface of the p-type semiconductor region 105. An n+ type high concentration region 115 is provided in a surface layer on the back surface side of the n− type semiconductor substrate. A cathode electrode 112 is provided in contact with the n+ type high concentration region 115. A portion sandwiched by the p-type semiconductor region 105 and n+ type high concentration region 115 is an n− type low impurity concentration region (hereafter referred to as an n− type low concentration region 102) remaining at the original impurity concentration of the n− type semiconductor substrate.
The n− type low concentration region 102, which forms a drift region, is adjusted so that the lifetime differs according to place. Specifically, the n− type low concentration region 102 includes first to third lifetime adjustment regions 102a to 102c adjusted to different lifetimes. The first lifetime adjustment region 102a is positioned to the p-type semiconductor region 105 side of the n− type low concentration region 102, in contact with the whole surface of the p-type semiconductor region 105. The third lifetime adjustment region 102c is positioned in the center of the device between the first lifetime adjustment region 102a and n+ type high concentration region 115. The second lifetime adjustment region 102b is adjacent to the third lifetime adjustment region 102c and surrounding the third lifetime adjustment region 102c, between the first lifetime adjustment region 102a and n+ type high concentration region 115. When comparing the lifetimes of each of the first to third lifetime adjustment regions 102a to 102c after lifetime adjustment, the lifetimes are such that the first lifetime adjustment region 102a<the second lifetime adjustment region 102b<the third lifetime adjustment region 102c. 
It is known that this kind of localized lifetime adjustment may be introduced by diffusing precious metal such as gold (Au) or platinum (Pt) selectively into a predetermined region, or by a selective irradiation of a predetermined region with radioactive rays such as electrons (for example, refer to International Publication No. WO 99/63597 (Page 15, Line 14 to Line 19)).
It is commonly known that a silicon semiconductor substrate can be doped to an n-type by an ion implantation of charged hydrogen (protons) followed by a low temperature annealing. The relationship between the proton dose and the impurity concentration after activation when the annealing conditions are 350° C. and 30 minutes, or the like, has already been published (for example, refer to D. Silber et al., “Improved Dynamic Properties of GTO-Thyristors and Diodes by Proton Implantation”, International Electron Devices Meeting (IEDM) Digest 1985, (U.S.A.), 1985, Volume 31, Pages 162 to 165)).
It is also already known that an n+ buffer layer of the IGBT is formed using a proton implantation and thermal annealing technology. Outlines of a typical device structure and doping profile of each portion are shown in FIG. 16 and FIG. 17 respectively. FIG. 16 is a sectional view showing a main portion of another example of a heretofore known IGBT. FIG. 17 is a doping profile diagram of the heretofore known IGBT of FIG. 16. After an IGBT surface structure (reference signs 25 to 29) is formed on the front surface of an n− type semiconductor substrate, and the n− type semiconductor substrate is thinned by grinding from the back surface, an n+ buffer layer 24 shown in FIG. 16 is formed by one or a plurality of proton implantations (for example, the three times NH1 to NH3 of FIG. 17) with an acceleration energy of 500 KeV or less, and a subsequent thermal annealing at a temperature of 300° C. to 400° C. for 30 minutes to 60 minutes. The proton dose and annealing conditions necessary to form the n+ buffer layer 24 are easily determined by referring to D. Silber et al., “Improved Dynamic Properties of GTO-Thyristors and Diodes by Proton Implantation”, International Electron Devices Meeting (IEDM) Digest 1985, (U.S.A.), 1985, Volume 31, Pages 162 to 165. The advantage of forming the n+ buffer layer 24 using a proton doping method is that the annealing temperature necessary to activate the n+ buffer layer 24 can be around approximately 350° C., which does not adversely affect a previously formed metal electrode film in the surface structure. With regard to reference signs not in the previous description of FIG. 16 and FIG. 17, reference sign 22 is an n− type drift region, reference sign 25 is a p-type base region, reference sign 26 is an n+ type emitter region, reference sign 27 is a gate dielectric, reference sign 28 is a gate electrode, reference sign 29 is an emitter electrode, reference sign 31 is a p− type collector region, and reference sign 32 is a collector electrode (for example, refer to U.S. Pat. No. 6,482,681 Description (FIG. 1, FIG. 6) and Japanese U.S. Pat. No. 4,128,777 (FIG. 1, FIG. 6)).
For the reverse blocking IGBT, when the gate is off and voltage is applied in a reverse direction (the collector electrode is connected to a lower electrostatic potential than the emitter electrode), there is sometimes a problem that large reverse leakage current occurs. FIG. 13 is an illustration showing a main portion sectional structure, and an electric field intensity profile when reverse direction voltage is applied, of a heretofore known reverse blocking IGBT. A simplified sectional view in a substrate vertical direction (the thickness direction of the semiconductor substrate) of a single cell, particularly the termination portion 110a and gate pad portion (not shown) thereof, in the active region 110 of FIG. 12 is shown on the left side of FIG. 13. The electric field intensity distribution when reverse direction voltage is applied is shown on the right side of FIG. 13. When reverse direction voltage is applied, a drift region 1-2 on the p-type collector region 10 side of the n− type drift region 1 is depleted along with the extension of a depletion layer from the collector junction (the p-n junction between the p-type collector region 10 and the n− type drift region 1), and a net n-type base 1-1 (a drift region on the p-type base region 2 side of the n− type drift region 1 that is not depleted) of a p-n-p transistor formed of a p-type emitter (the p-type base region 2), an n-type base (the n− type drift region 1), and the p-type collector region 10 becomes thinner. Furthermore, combined with the p-type emitter concentration being high and the injection efficiency thereof also being high, the leakage current generated in the depletion layer region (the drift region 1-2) is amplified by the p-n-p transistor, and the device leakage current increases, as a result of which there is a problem that the element operating temperature (heat resistance) is limited.
Also, in the event that reverse direction voltage is applied in a state wherein collector quality is low, such as when there are a large number of defects in the p-type collector region 10, or in a state wherein the p-type collector region 10 boron dose is too small, there is a concern that the depletion layer spreading from the p-n junction between the p-type collector region 10 and n− type drift region 1 also spreads to the thin p-type collector region 10 side, and could punch through to the collector electrode 11. In which case, the reverse leakage current increases significantly. In order to overcome this kind of problem of the reverse leakage current increasing, it is known to be preferable that the p-type collector region 10 is locally highly activated using a YAG laser (for example, refer to JP-A-2007-59550 (Paragraph 0009)). Also, it is also known that, in order to suppress an increase in switching loss due to the remaining of highly injected hole carriers from the p-type collector region 10 accompanying the localized high activation of the p-type collector region 10, it is good when the annealing temperature after electron irradiation is kept low at around 330° C., thus reducing the lifetime of the n− type drift region 1.
Also, there is a description relating to a reverse blocking IGBT wherein, by providing a lifetime killer layer inside a drift region near a collector region, the reverse recovery peak current of the reverse blocking IGBT operated as a diode is reduced, thus imparting soft recovery characteristics (for example, refer to JP-A-2002-76017 (Abstract, FIG. 1)).
Also, there is also known technology relating to a diode wherein, by providing a high concentration region in a central portion of the thickness of a drift region using proton irradiation, an increase in dV/dt when there is reverse recovery is suppressed, thus imparting soft recovery characteristics (for example, refer to JP-A-2009-224794 (Abstract, FIG. 1)).
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.